1. Field of the Invention
The present invention relates to a semiconductor memory device which rewritably stores data in a plurality of memory cells formed at intersections of a plurality of word lines and a plurality of bit lines, and particularly relates to a semiconductor memory device in which a memory cell array having a hierarchical structure is configured with a unit including a predetermined number of local bit lines and one global bit line.
2. Description of the Related Art
In a general DRAM, there are provided a memory cell array including memory cells formed at intersections of bit lines and word lines, and a large number of sense amplifiers for amplifying data of the memory cells. In recent years, as the capacity of the DRAM becomes large, an extremely large number of memory cells are connected to each bit line, thereby causing performance problems due to an increase in parasitic capacitance and resistance of the bit line. Further, a configuration in which a large number of memory cells can be arranged in an extremely small area is desired. Under such a back ground, various configurations in which a memory cell array including a hierarchical structure of global bit lines and local bit lines partitioned into sections are proposed (e.g., see Patent References 1 to 4). By employing the memory cell array having such a hierarchical structures the memory cells can be arranged on the local bit line whose length is shorter than that of the global bit line, and a configuration advantageous for reducing parasitic capacitance and resistance can be achieved.
Patent Reference 1: Japanese Patent No. 3521979
Patent Reference 2: Japanese Patent No. 3529534
Patent Reference 3: Published Japanese Translation No. H10-512085
Patent Reference 4: Patent Application Laid-open No. 2000-57761
In order to obtain the advantage of employing the local bit lines, it is desirable to use single-ended sense amplifiers instead of using differential sense amplifiers. Since the single-ended configuration reduces the circuit scale relative to the differential configuration, an increase in the entire area can be suppressed even when sections to which the local bit lines are partitioned are increased.
However, among the above configurations for the hierarchical memory cell array, Patent References 1 to 3 disclose that the sense amplifiers are not directly connected to the local bit lines while connected to the global bit line. As described above, when employing the single-ended sense amplifiers, it is difficult to amplify a minute potential difference, as different from using the differential sense amplifiers. On the other hand, in the configuration where a signal reaches the sense amplifier via both the local bit line and the global bit line, the length of the bit line becomes long and it becomes a problem that operating performance deteriorates due to the influence of the parasitic capacitance and resistance. Meanwhile, in the Patent Reference 4, there is disclosed a configuration in which sense amplifiers connected to local bit lines of a folded bit line structure. However, since memory cells are arranged only at half of intersections of word lines and local bit lines, it is difficult to improve the integration of the memory cell array. Further, this configuration requires the differential sense amplifier connected to a complementary pair of local bit lines, and thus the required area is increased.